Loogikatehekood Project Status (05/29/2014 - 17:27:17)
Project File: Loogikatehe.xise Parser Errors: No Errors
Module Name: Loogikatehekood Implementation State: Synthesized
Target Device: xc3s100e-4cp132
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 0 960 0%
Number of bonded IOBs 5 83 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentN 29. mai 17:18:14 2014000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateR 16. mai 17:52:22 2014
Post-Synthesis Simulation Model ReportCurrentN 29. mai 17:27:16 2014

Date Generated: 05/29/2014 - 17:27:17