counter_1 Project Status (05/29/2014 - 17:10:56)
Project File:	counter_1.xise	Parser Errors:	No Errors
Module Name:	counter_1	Implementation State:	Programming File Generated
Target Device:	xc3s100e-4cp132	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	12	1,920	1%
Number of occupied Slices	8	960	1%
Number of Slices containing only related logic	8	8	100%
Number of Slices containing unrelated logic	0	8	0%
Total Number of 4 input LUTs	12	1,920	1%
Number of bonded IOBs	37	83	44%
IOB Flip Flops	4
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	0.91

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	N 29. mai 16:52:28 2014	0	0	0
Translation Report	Current	N 29. mai 17:07:02 2014	0	0	0
Map Report	Current	N 29. mai 17:07:06 2014	0	0	2 Infos (0 new)
Place and Route Report	Current	N 29. mai 17:07:34 2014	0	0	1 Info (0 new)
Power Report
Post-PAR Static Timing Report	Current	N 29. mai 17:07:37 2014	0	0	6 Infos (0 new)
Bitgen Report	Current	N 29. mai 17:10:47 2014	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
Post-Map Static Timing Report	Current	N 29. mai 17:07:09 2014
Post-Map Simulation Model Report	Current	N 29. mai 17:07:20 2014
WebTalk Report	Current	N 29. mai 17:10:48 2014
WebTalk Log File	Current	N 29. mai 17:10:55 2014

Date Generated: 05/31/2014 - 21:16:23