regtootleminekood Project Status (05/29/2014 - 17:37:09)
Project File:	regtootlemine.xise	Parser Errors:	No Errors
Module Name:	regtootleminekood	Implementation State:	Programming File Generated
Target Device:	xc3s100e-4cp132	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	2 Warnings (2 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	8	1,920	1%
Number of occupied Slices	6	960	1%
Number of Slices containing only related logic	6	6	100%
Number of Slices containing unrelated logic	0	6	0%
Number of bonded IOBs	5	83	6%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	1.50

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	N 29. mai 17:34:35 2014	0	2 Warnings (2 new)	0
Translation Report	Current	N 29. mai 17:36:42 2014	0	0	0
Map Report	Current	N 29. mai 17:36:46 2014	0	0	2 Infos (2 new)
Place and Route Report	Current	N 29. mai 17:36:53 2014	0	0	2 Infos (2 new)
Power Report
Post-PAR Static Timing Report	Current	N 29. mai 17:36:56 2014	0	0	6 Infos (6 new)
Bitgen Report	Current	N 29. mai 17:37:01 2014	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	N 29. mai 17:37:01 2014
WebTalk Log File	Current	N 29. mai 17:37:09 2014

Date Generated: 05/29/2014 - 17:37:09